Phillip Corson and Scott Decker – Subject Matter Experts in On-Wafer-Device-Test and Failure Analysis Launch Powerful New Group: On-Wafer-Device-Test
On-wafer-device-test Guru Leads SMARTvt’s OWDT Consulting Division providing one-of-a-kind Test evaluations for clients.
Click to Join Group: http://www.linkedin.com/groups?home=&gid=5138053&trk=anet_ug_hm
On-Wafer-Device-Test – A Powerful Group Alliance and Lobby and Technology Growth Group
On-Wafer-Device-Test: Dedicated to the idea that Improved Testing Processes, Sharing Test Process Ideas, Exploring and Developing New Test Process Technologies Hardwares, Software, Nanotechnologies and others, Educative Dialogue of Test Processes, Meaningful Interactive (Lobby) Government and Economic Development Ideation of Test Process Technologies as an Industry, Combining Strategic Human Resources Capital specific to Test Process Technologies, results in the betterment in the ways the world lives.
Who wants to join On-Wafer-Device-Test
– Engineers at all levels
– Professionals interested in extreme range differentiation testing
– Technology Human Resources Professionals
– Professional who make Test Apparatuses and Technologies
– Professionals who code softwares for testing
– Economic Development Professionals Seeking Job Creation Ideas
– Lobbyist, Grantors, Government Officials Concerned About Workforce Development
– On-Wafer-Device-Test Professionals
– Equipment Makers of Test Products
– Users of end products that require testing
– Subject Matter Experts: Test
– Business Planners Who Need Test Professionals as Resource
– Chief Technology Officers who seek crowd sourcing to solve complex problems
– Chief Executive Officers who need to read materials to stay ahead of the curve
– Chief Financial Officers who need expertise in balancing People, Technology, and Profitability
SMARTvt - SMART Holdings USA 
We need to start a discussion on changing the way we test. Silicon and Packaging Integration scaling is on the horizon. Things like 3D , Photonics on Si , and a dramatic increase in mixed signal applications, and heterogenious designs and technologies on 3D interposers will drive new test solutions into the fabs of the future. Tests we did at systems, board, and package level will be done on Silicon. New Probe, contacting, pick and place, handling, and aligment systems will be needed to handle and contact agressive scaling and thin silicon. New thermal solutions will be needed. DLT ( die level test ) will be a bigger part of the conversation that offers 100% mechanical and electrical asyncronous test with many advantages over traditional wafer level test. Test Cost and improved test system efficiency will be front and center of every technical solution. High Speed test and 100 % AC and DC KGD test coverage at silicon level will be required before 3D stacking. This is already part of the conversation at test conferences in 2013. Tester integration and scaling will be dramatic which will include active test probes being used as the tester. All of the next generation semiconductors will require significant new test paradigms and major shifts in the way we think about test.
Good Luck!!
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